1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
Conventionally, DRAM (Dynamic Random Access Memory) circuits have been known as semiconductor memory devices. FIG. 10 shows schematic plane view of a DRAM circuit chip 1. As shown in FIG. 10, the DRAM circuit chip 1 is composed of memory array regions 2, sense-amplifier regions 3, word-line driver regions 4, and intersection regions 5. The memory array regions 2 have a plurality of memory cells arranged in a matrix. A word line and a bit line are connected to each memory cell. The word line is driven by a word-line driver located in the word-line driver region 4. The bit line is connected to a sense-amplifier circuit located in the sense-amplifier region 3, and the sense-amplifier amplifies a potential between a pair of bit lines. The intersection regions 5 are regions at which the sense-amplifier regions and the word-line driver regions 4 intersect each other.
In recent years, the reduction of chip areas has been desired in semiconductor memory devices in order to downsize the devices and lower the manufacturing costs. Japanese Unexamined Patent Application Publication No. 2004-221374 (Patent document 1) discloses a semiconductor memory device as a technique to reduce the chip area. The object of the semiconductor memory device disclosed in Patent document 1 is to reduce the size of sense-amplifier regions between memory cell arrays, i.e., regions corresponding to the sense-amplifier regions 3 in FIG. 10.
FIG. 11 shows a schematic plane view in and around a sense-amplifier region 3 of a DRAM circuit chip 10 of a semiconductor memory device disclosed in Patent document 1. Furthermore, FIG. 12 shows a circuit diagram of a typical sense amplifier, which is also used in Patent document 1. Firstly, the circuit configuration of a sense amplifier SA1 shown in FIG. 12 is explained hereinafter. As shown in FIG. 12, the sense amplifier SA1 includes PMOS transistors QP1 and QP2, and NMOS transistor QN1 and QN2. Since the sense amplifier SA1 is a typical sense amplifier and its operation and configuration are well known, its explanation is omitted. The source of each PMOS transistors QP1 and QP2 of the sense amplifier SA1 is connected to a node A. The source of each NMOS transistors QN1 and QN2 is connected to a node B. Sense amplifiers SA2, . . . , each of which has a similar configuration to that of the sense amplifier SA1, are also connected between these nodes A and B. Furthermore, a PMOS transistor QP3 is connected between a power-supply voltage terminal VDD and the node A. An NMOS transistor QN3 is connected between a ground voltage terminal GND and the node B. These PMOS transistor QP3 and NMOS transistor QN3 are driver transistors that drive the sense amplifiers SAT, SA2, . . . . Note that sense-amplifier control signals SEP and SEN are input to the PMOS transistor QP3 and NMOS transistor QN3 respectively in order to control their On-states and Off-states.
A boundary line 50 in FIG. 11 separates an N-well region 20, above which the above-described PMOS transistors QP1 to QP3 are formed, from a P-well region 30, above which the above-described NMOS transistors QN1 to QN3 are formed. Note that in practice, the boundary line 50 is formed as an element separation region composed of a silicon dioxide film or the like. The PMOS transistors QP1 and QP2 shown in FIG. 12 are formed in regions 21 in FIG. 11. Furthermore, the PMOS transistor QP3 is formed in a region 22 in FIG. 11. Meanwhile, the NMOS transistors QN1 and QN2 shown in FIG. 12 are formed in regions 31 in FIG. 11. Furthermore, the NMOS transistor QN3 is formed in a region 32 in FIG. 11. Furthermore, contacts 41 and 42 that supply well potentials to the respective wells are formed between the driver transistors. By using such a configuration, the width L10 of the sense-amplifier region 3 is shortened and thus reducing the size of the sense-amplifier region 3.
Furthermore, Patent document 1 also discloses another technique in which the size of the sense-amplifier regions 3 is reduced by disposing the driver transistors in the intersection regions 5 of the sense-amplifier regions 3.